And this from the MSB Diamond DAC V Manual
Clock Interface
After years of experimenting with inputting and outputting clocks we now strongly recommend not doing this. A low jitter clock must be physically close to the DACs. There is no lower jitter clock than the MSB clocks, and even if there were, once the clock was transmitted from an external box so much jitter would be introduced in the cable that the clock would be marginal at best. So we are confident that no benefit would be gained from an external clock.
A different set of problems exist with outputting clocks. A paradox is created as a source needs a clock to transmit data, but when the DAC sees the data, which can be at any sample rate, it adjusts the clock to match. No source can handle its clock adjusted on the fly. Only the MSB Transports can handle this as the PRO I2S interface is smart and negotiates the proper clock to be sent back to the transport. But, if you do have a need to access this clock, it can be done.
Within the MSB Network connection is a clock interface that allows multiple Platinum products to be synchronized, allows the Plati- num Clock to be input or output. The interface is a LVDS format clock interface with a signal level of 250 mV pp.
Pin Identification - The pins shown in the figure below are identified as follows: 1. M Clock + (Positive side of balanced Master Clock)
2. M Clock - (Negative side of balanced Master Clock)
Clock Frequencies - The clock can be selected to be either an input, output or turned off in the setup menu. The output frequencies are as follows:
· 44.1, 88.2 or 176.4 kHz sampling frequency source outputs or inputs a clock frequency of 22.5792 MHz · 48, 96 or 192 kHz sampling frequency source outputs or inputs a clock frequency of 24.576 MHz.