Thanks for your input. My personal opinion is that, the weakest link of the AN kits, and for that matter, even the high end UK AN DACs (like the 5), is the digital implementation overall. I've heard an AN DAC 5 in demo, and from what I recall, it doesn't come across as a "modern" design, in that modern designs try to keep all the attributes of analog, while preserving the detail and dynamic ability that could be achieved with modern digital. I know the UK DAC 5 uses really nice parts, but the digital board is still using the decades old Cirrus PCM chipset (or something equivalent.. can't tell for sure what exactly is there because I never owned one or opened the hood). These digital implementations based upon older tech are missing substantial improvements in jitter reduction. In addition, there are much better, low noise, lower impedance shunt regulators available to be used with the DAC IC, which I think is also far out of date on the stock kit or UK implementation.
Any current source (like the output of the DAC IC) wants to see a ground, or virtual ground (no voltage rise, full current shunt), hence, the popularity of opamp based I-V conversion. Considering the relatively low output impedance of the DAC chip with its R2R implementation, passive loading via proper resistor value becomes even more critical. With a single DAC chip, a relatively high load resistor value needs to be used to generate acceptable voltage output. Parallel DAC chips, although not really improving the current source situation from an individual DAC chip point of view, does allow you to closer approach a short circuit load for the current source output (ie, lower load resistance to generate the same output voltage because the total current has been increased by N number of chips). Dropping the value of the load resistor increases linearity at the high signal level side, and the increased current improves noise immunity at the lower signal level side. In addition, my guess is the slew rate of the output decreases during fast and large transients (high dV/dt) due to less drive capability as the output terminal voltage increases, which is also partially rectified with parallel chips. Using a balanced approach at the I-V conversion stage, in addition to subtracting out even order harmonics, does help reduce overall dither like noise from the DAC output and also some common mode power supply noise. Attempting to address all these issues translates into "better", more realistic sound (quieter, more dynamic, more linear, and more resolving). I'm assuming these are the areas where the Kassandra excels relative to an AN DAC. In short, trying to address all these aspects should yield the biggest returns on the ANK platform, which is my goal
I'm a believer in stout power supply design, however, there is such a thing as "too much" reserve capacitance. Too much doesn't necessarily produce any negative side effects, but it also doesn't produce increasingly positive effects either. A DAC just doesn't draw as much dynamic power as a power amp would. A power supply should be designed for ample reserve capacity from the wall, through the power transformer, and into the power supply reserves (overall bulk capacitance). Its not too difficult to attain plenty of total reserve capacity and get it all charged up, but the "quality" of the reserve is important (ie, low ESR). Charging the reserve bank of capacitance is one thing, but the ability for a demanding load to draw/discharge upon these reserves quickly and without lag (at the frequencies of current demand, which will vary based upon the load circuit) is more important to good power supply design. Low power supply impedance across frequencies of interest for local decoupling capacitors also plays into this. No doubt, the Kassandra has already hit on all of these subjects. But, my point is, comparing overall total of bulk capacitance does not automatically imply a better power supply.
As far as the Kassandra, if all that you guys are using is NOS (44.1kHz), if your Pulsar reference clock is not the lowest possible common denominator frequency to support the related MCLK rate, then I would inquire with the designer on if the Pulsar OCXO could be swapped to a lower frequency (depending upon his overall implementation). There is a huge improvement in phase noise for lower frequency crystals (just physics). For example, if the current reference clock is 45.1584MHz, you may be able to use a /2 or /4 crystal (for only 44.1kHz), and get a huge improvement in your sound. That is, at this already low jitter level overall, if you could perceive further jitter level improvements. Also, this assumes the DAC chip itself sounds the same at different rates, which maybe it doesn't. It would be something worth asking about though.