While looking over this, I realized I never got back on a question about voltages along the line and at the ends (source and load). Here are a couple of quick pictures that might help...
First, the test system. This is a very simple test, just an ideal source with real (resistor) output impedance, a transmission line, and resistor load. For this example, the source and transmission line impedances are both 100 ohms, and we'll vary the load. The source outputs a 100 ns pulse 2 V high. These are arbitrary, just making life easy. The transmission line is 20 ns long (about 9.5 feet for the parameters I plugged in; again, immaterial to this post).
This first picture is with a matched load (ZL = 100 ohms). The source pulse (solid red line) starts at zero and ends at 100 ns as expected. At the transmission line (SOURCE), the voltage is divided by two since half the voltage is dropped across the source resistor, and the other half across the transmission line. At the middle of the line, the pulse (MIDLINE, dotted brown) rises to 1 V 10 ns after the start of the pulse as expected. This is the travel time for the pulse from the source to reach the middle of the line. The load (LOAD, dashed blue) sees the start of the pulse 10 ns later, or 20 ns from the time the source pulse first hit the transmission line. Since everything is perfectly matched, there are no reflections, and the pulse dies away cleanly.
Now, to take an extreme case, what happens if the load is open (infinite ohms)? Now, starting out there is a voltage divider with the transmission line as before, but when the pulse hits the end of the line (at 20 ns) there is nowhere for the extra current to go (no load), and the voltage steps up to the open-circuit voltage, 2 V. Wow, twice the voltage! Not twice the power, however, conservation of energy and all that, and since the load cannot absorb any energy (it is an open), the pulse is reflected back toward the source.
Now, 20 ns later, or 40 ns after the starting edge, the reflected pulse from the load hits the source end of the line. This now doubles the voltage at the source end, stepping up to 2 V (1 V from the source plus 1 V from the reflected wave). At 100 ns, the source turns off, and the voltage drops to 1 V, all from the reflected wave. Then 40 ns after
that, all the initial pulse has traveled to the load and back, and the system is back at 0 V.
Now, if this was a real system, with a real clock signal (pulse train), complex impedances, and no perfect matching anywhere, you could end up with a very complicated plot, with all sorts of ripples and different edges at different times from all the different reflected waves running around. The signal at any given time is a function of current (that is, present-time) and previous signals, the length of the line, and all the different impedances (source, line, load, including connectors and whatnot). That sort of thing can cause sampling errors because the clock no longer has single, clean edges during each cycle.
No wonder buffering and re-clocking with a known-good clock signal is so popular!
Hope this helps - Don