New EtheREGEN Gen2

Stereophonic

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Jun 9, 2013
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Hi everybody.
Uptone writes in its site:

We are still hard at work on EtherREGEN Gen2—utilizing more readily available parts and incorporating a number of technical advancements. These include Gigabit capability on both the ‘A’ and ‘B’ sides of our unique active-differential-isolation moat, even lower jitter clock synthesizers, new PHY chips, and the world’s best sine-to-square wave converter (benefiting those who chose to pair with an external 10MHz reference clock). The new version will even include a second SFP cage—on the ‘B’ side—to improve performance for users of optical endpoints. A challenging engineering puzzle--with the new high-performance, low-jitter PHY chip that we have chosen--has been solved at long last! Now we can finally move forward with the "unified" design, bringing all elements together. However, one more development board must be finished before we can produce a final set of pre-production/beta boards. This progression will take a few more months--therefore we now expect first shipment of EtherREGEN Gen2 will not take place until June 2025. Thank you for your patience and enthusiasm. (Please note that we will not be taking any trade-ins to upgrade to Gen2. Different circuit board, different case, and we can not resell used products.​

Anybody knows anything more about this new switch?
 
Hi everybody.
Uptone writes in its site:

We are still hard at work on EtherREGEN Gen2—utilizing more readily available parts and incorporating a number of technical advancements. These include Gigabit capability on both the ‘A’ and ‘B’ sides of our unique active-differential-isolation moat, even lower jitter clock synthesizers, new PHY chips, and the world’s best sine-to-square wave converter (benefiting those who chose to pair with an external 10MHz reference clock). The new version will even include a second SFP cage—on the ‘B’ side—to improve performance for users of optical endpoints. A challenging engineering puzzle--with the new high-performance, low-jitter PHY chip that we have chosen--has been solved at long last! Now we can finally move forward with the "unified" design, bringing all elements together. However, one more development board must be finished before we can produce a final set of pre-production/beta boards. This progression will take a few more months--therefore we now expect first shipment of EtherREGEN Gen2 will not take place until June 2025. Thank you for your patience and enthusiasm. (Please note that we will not be taking any trade-ins to upgrade to Gen2. Different circuit board, different case, and we can not resell used products.​

Anybody knows anything more about this new switch?
I’m sure that @Superdad has insight.
 
Any more updates? It's already nearing end Sept 2025
As it happens, I did post an update--in the EtherREGEN thread on our sponsored forum at AS--about our progress on Monday. Here is what I posted:

Just arrived: Yet another sub-set test board on the long road of EtherREGEN Gen2 development.
This one should fix some long-overlooked issues with voltage timing/resets and with the programming interface between our new main switch chip and our new PHY.


And as long as we're spending the $$ on a pair of these boards ($2,600 + $430 tariffs
¬¬
) we went ahead and are using/testing new 1A ultra performance linear regs which are a slight advancement over the 500mA LT3045s. 2x the current capability means we can use many fewer (there were 13 LT3045/42 on the original and those are now more than $5 each); plus they are more readily available and run cooler.

Again, this board is NOT an EtherREGEN Gen2 in the least. It is simply a (hopefully) final pass at solving the switch chip > PHY chip SGMII link issue which has been slowing us down for 18 months. In a couple of days all those header pins you see sticking up will have all manner of test gear probe leads attached. Assuming my partner John Swenson has success with this board we will quickly move onward towards the "unified" design containing all our new clock synth circuits, the isolator chips, our special differential flip-flops, the 'A' side PHY, second SFP cage, etc.

Wish us luck!

ER2 QAtest V0995.jpeg
 
Good luck, Alex!
 
Thanks for your enthusiasm.
I’m traveling today but planning to post a very good news update this coming week. The above pictured subset test board—after a couple of small tweaks—is a success! At long last our new main switch chip and new PHY chip are fully negotiating/communicating in SGMII at all speeds.

We can now move onwards towards the “unified” design, though probably two rounds of boards will be needed—to test some advanced things—before we do a final pre-production/beta user pool run.

Once I have some sessions with John Swenson to plan these next boards, as well as checking to be sure that all our preferred parts (beyond the $90K in chips I have been sitting on here for 2+ years) are going to be available—I’ll be able to timeline out our path to full production. Until then I’m not ready to hazard a guess at a date.

But now that all the bedeviling riddles have been solved, there should be no unknown obstacles to prevent EtherREGEN Gen2 from happening in the coming few months.
It is sure to be amazing! :cool:
 
Great news @Superdad !

10MHz support, two spf ports separated by an isolator, is it still in force in the final design?
 

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